1. Field of the Invention
This invention relates to a method of increasing the yield and reliability of integrated circuit chips manufactured from gate arrays and, more particularly, to an improved method of designing and implementing metallization patterns for such gate arrays.
2. Description of the Prior Art
As will be appreciated by those skilled in the art, the so-called gate array (also referred to in the art as a masterslice) approach is widely used to produce semiconductor integrated circuit chips. Gate array refers to an array (matrix) of devices, such as resistors and transistors, that can be connected as logic gates. In a gate array process, a fixed number of uncommitted and unconnected devices are pregrouped into a cell. A number of identical cells are arranged in rows and columns on a chip, with space between and above them reserved for interconnections. This allows a large number of identical wafers to be fabricated and later personalized in different ways to fabricate specific chip functions. To implement a specific chip function, a designer specifies circuit functions and their interconnects, and a computer-aided design program specifies the metallization data that will make the connections between the circuits to implement the desired chip function in the array. Programs are available to generate metallization data for forming photolithographic masks and for direct write electron beam fabrication.
FIG. 1 illustrates a typical prior art gate array computer design program to which the teachings of this invention are applicable. The program elements include a Circuit Library, a Gate Array Description, a Chip Functional Description and Fixed Metal.
The Circuit Library contains a computer stored data base of metallization data required to implement individual logic functions (e.g., OR, AND, XOR, etc.) from the devices in a gate array cell.
The Gate Array Description is a stored data image, describing cell locations, allowed interconnect paths and areas reserved for power bussing.
The Chip Functional Description is a database of circuit functions and their interconnects required to perform the chip function prescribed by a designer for a specific application.
The Fixed Metal is a database of metallization data required to provide power to all cell locations on a chip, thus allowing all possible circuit placements. Here it should be noted that, due to density optimization of gate array cell designs, non-symmetries exist in the cells. These are usually restricted to the power supply distribution in the Fixed Metal.
In a Placement step, the computer aided design program optimally places the required circuits in the gate array cells, as dictated by the Chip Functional Description.
A Wiring step uses maze routing code to describe physical interconnections between placed circuits as prescribed by the Chip Functional Description. The output of the Wiring step is metallization data specifying a pattern of wires and inter-level via connections referred to as Global Metal.
A step called Shapes Creation and Check includes Combine and Pattern Creation steps in which the circuit, global and fixed metallization data are combined to create an output for forming the complete metallization pattern.
The value of a gate array only exists when all logic elements properly process signals from chip inputs to chip outputs. Thus, the metallization pattern must exist without fault. The Fixed Metal in the gate arrays must be designed to accept any circuit since, prior to the Placement step, it is unknown which circuit will be placed in a particular cell. In particular, since any cell may be occupied, the Fixed Metal must supply power to all cell locations. If the Fixed Metal does not satisfy the circuit requirements in all cells, a non-functional product could result.
The advantages of gate arrays over fully customized cells are: shorter design turnaround time, low cost through mass production of non-personalized gate array chips, the need for fewer masks, and shorter fabrication time since only the final metallization pattern and contact layers need to be customized. A disadvantage is wasted chip area, which results from the fact that, in general, all cells are not used. Moreover, the Fixed Metal provided to unused cells to support general applications becomes a source for yield and reliability reductions. A prior art method of reducing Fixed Metal in gate arrays involves photolithographic removal of the Fixed Metal after chip fabrication. However, this method is undesirable due to the increase in overall time and process complexity.
FIGS. 2A and 2B show a schematic diagram of a logic gate and a pictorial representation of this logic gate implemented on a typical gate array cell. The Fixed Metal is represented by the cross-hatched areas. The Circuit Metal is represented by clear shapes. An unused fixed metal shape 1 is one which does not contact circuit metal 3. Certain individual circuit types require only portions of the total power supplied to each cell. Also gate array chips typically do not place circuits in all cells. Hence, excess Fixed Metal exists for cells which contain placed circuits as well as for entire cells.